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STK14CA8
128Kx8 AutoStoreTM nvSRAM
Features

Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvolatile QuantumTrapTM storage element included with each memory cell. This SRAM provides fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Cypress nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performing and most reliable nonvolatile memory available.
25, 35, 45 ns Read Access and Read/Write Cycle Time Unlimited Read/Write Endurance Automatic Nonvolatile STORE on Power Loss Nonvolatile STORE Under Hardware or Software Control Automatic RECALL to SRAM on Power Up Unlimited RECALL Cycles 200K STORE Cycles 20-Year Nonvolatile Data Retention Single 3.0V + 20%, -10% Operation Commercial and Industrial Temperatures Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Logic Block Diagram
VCC A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Quantum Trap 1024 X 1024 ROW DECODER STORE STATIC RAM ARRAY 1024 X 1024 RECALL STORE/ RECALL CONTROL VCAP
POWER CONTROL
HSB
SOFTWARE DETECT INPUT BUFFERS COLUMN I/O COLUMN DEC
A15 - A0
A0 A1 A2 A3 A4 A10 A11
G E W
Cypress Semiconductor Corporation Document Number: 001-51592 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 04, 2009
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STK14CA8
Pinouts
Figure 1. 48-Pin SSOP
VCAP A16 A14 A12 A7 A6 A5 NC A4 NC NC NC VSS NC NC DQ0 A3 A2 A1 A0 DQ1 DQ2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB W A13 A8 A9 NC A11 NC NC NC VSS NC NC DQ6 G A10 E DQ7 DQ5 DQ4 DQ3 VCC
Figure 2. 32-Pin SOIC
VCAP A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 HSB W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 3. Relative PCB Area Usage[1]
Pin Descriptions
Pin Name A16-A0 DQ7-DQ0 E W G VCC HSB I/O Input I/O Input Input Input Power Supply I/O Description Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. Data: Bi-directional 8-bit data bus for accessing the nvSRAM. Chip Enable: The active low E input selects the device. Write Enable: The active low W allows to write the data on the DQ pins to the address location latched by the falling edge of E. Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. Power: 3.0V, +20%, -10%. Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection is optional). AutoStoreTM Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. Ground. Unlabeled pins have no internal connections.
VCAP VSS NC
Power Supply Power Supply No Connect
Note 1. See Package Diagrams on page 15 for detailed package size specifications.
Document Number: 001-51592 Rev. **
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STK14CA8
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................-0.5V to 4.1V Voltage on Input Relative to VSS ...........-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB ......................-0.5V to (VCC + 0.5V) Temperature under Bias ............................... -55C to 125C Junction Temperature ................................... -55C to 140C Storage Temperature .................................... -65C to 150C Power Dissipation............................................................. 1W DC Output Current (1 output at a time, 1s duration).... 15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS jc 5.4 C/W; ja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm]. RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS jc 6.2 C/W; ja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]. Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Characteristics
(VCC = 2.7V to 3.6V) Symbol ICC1 Parameter Average VCC Current Commercial Min Max 65 55 50 Industrial Min Max 70 60 55 Units Notes
mA tAVAV = 25 ns mA tAVAV = 35 ns mA tAVAV = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. mA All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE)
ICC2
Average VCC Current during STORE Average VCC Current at tAVAV = 200 ns 3V, 25C, Typical Average VCAP Current during AutoStore Cycle VCC Standby Current (Standby, Stable CMOS Levels)
3
3
ICC3
10
10
mA W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads.
ICC4
3
3
ISB
3
3
mA E (VCC -0.2V) All Others VIN 0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete A A V V V V VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G All Inputs All Inputs IOUT = - 2 mA IOUT = 4 mA 3.3V + 0.3V
mA All Inputs Don't Care Average current for duration of STORE cycle (tSTORE)
IILK IOLK VIH VIL VOH VOL TA VCC VCAP NVC DATAR Note
Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE operations Data Retention 0 2.7 17 200 20 2.0 VSS-0.5 2.4
1 1 VCC+0.3 0.8 0.4 70 3.6 120 -40 2.7 17 200 20 2.0 VSS-0.5 2.4
1 1 VCC+0.3 0.8 0.4 85 3.6 120
VIH
C
V F K Years At 55 C Between VCAP pin and VSS, 5V rated.
The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested. Page 3 of 16
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STK14CA8
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times ................................................. 5 ns Input and Output Timing Reference Levels .................... 1.5V Output Load..................................See Figure 4 and Figure 5
Capacitance
(TA = 25C, f = 1.0 MHz) Symbol CIN COUT Parameter[2] Input Capacitance Output Capacitance Max Units 7 7 pF pF Conditions
V = 0 to 3V V = 0 to 3V
Figure 4. AC Output Loading
3.0V
577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Figure 5. AC Output Loading for Tristate Specifications (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
3.0V
577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE
Note 2. These parameters are guaranteed but not tested.
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STK14CA8
SRAM READ Cycles #1 and #2
NO. #1
1 2 3 4 5 6
Symbols Parameter #2 tELQV tAVAV[3] tAVQV
[4]
STK14CA8-25 STK14CA8-35 STK14CA8-45 Min Max 25 25 25 12 3 3 10 0 10 0 25 0 35 0 13 0 45 3 3 13 0 15 35 35 15 3 3 15 Min Max 35 45 45 20 Min Max 45
Units ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
tELEH[3] tAVQV
[4]
tGLQV tAXQX
[4]
tAXQX tELQX
[4]
7
tEHQZ[5] tGLQX tGHQZ[5] tELICCH[2] tEHICCL[2]
8 9 10 11
Figure 6. SRAM READ Cycle #1: Address Controlled[3, 4, 6]
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT)
DATA VALID
3 tAVQV
Figure 7. SRAM READ Cycle #2: E and G Controlled[3, 6]
2 1 6
29 11
7 3 9 4 8
10
Notes 3. W must be high during SRAM READ cycles. 4. Device is continuously selected with E and G both low 5. Measured 200mV from steady state output voltage. 6. HSB must remain high during READ and WRITE cycles
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STK14CA8
SRAM WRITE Cycles #1 and #2
NO.
12 13 14 15 16 17 18 19 20 21
Symbols #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ[5,7] tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ
Parameter Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Setup to End of Write Data Hold after End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold after End of Write Write Enable to Output Disable
STK14CA8-25 STK14CA8-35 STK14CA8-45 Min 25 20 20 10 0 20 0 0 10 3 3 Max Min 35 25 25 12 0 25 0 0 13 3 Max Min 45 30 30 15 0 30 0 0 15 Max
Units ns ns ns ns ns ns ns ns ns ns
tOW Output Active after End of Write
Figure 8. SRAM WRITE Cycle #1: W Controlled[7,8]
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
21 tWHQX
Figure 9. SRAM WRITE Cycle #2: E Controlled[7,8]
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
Notes 7. If W is low when E goes low, the outputs remain in the high impedance state. 8. E or W must be VIH during address transitions.
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STK14CA8
AutoStore/POWER UP RECALL
NO.
22 23 24 25
Symbols Standard Alternate tHRECALL tSTORE VSWITCH VCCRISE tHLHZ
Parameter Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time
STK14CA8 Min Max 20 12.5 2.65 150
Units ms ms V s
Notes 9 10, 11
t
Figure 10. AutoStore/POWER UP RECALL
25
23
23
22
22
Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Notes 9. tHRECALL starts from the time VCC rises above VSWITCH 10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place 11. Industrial Grade devices require maximum 15 ms.
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STK14CA8
Software Controlled STORE/RECALL Cycle
NO.
26
Symbols E Cont G Cont tAVAV tAVEL tELEH tEHAX tAVAV tAVGL tGLGH tGHAX Alt tRC tAS tCW
Parameter[12,13] STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration
STK14CA8-35 STK14CA8-35 STK14CA8-45 Min 25 0 20 1 50 Max Min 35 0 25 1 50 Max Min 45 0 30 1 50 Max
Units Notes ns ns ns ns s 13
27 28 29 30
tRECALL tRECALL
Figure 11. Software STORE/RECALL CYCLE: E Controlled[13]
26 26
27
28
29
23
30
Figure 12. Software STORE/RECALL CYCLE: G Controlled[13]
26 26
27
28
23 29
30
Notes 12. The software sequence is clocked on the falling edge of E controlled READs or G controlled READs 13. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
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STK14CA8
Hardware STORE Cycle
NO.
31 32
Symbols Standard tDELAY tHLHX Alternate tHLQZ
Parameter Hardware STORE to SRAM Disabled Hardware STORE Pulse Width
STK14CA8 Min 1 15 Max 70
Units s ns
Notes 14
Figure 13. Hardware STORE Cycle
32
23
31
Soft Sequence Commands
NO.
33
Symbols Standard tSS
Parameter Soft Sequence Processing Time
STK14CA8 Min Max 70
Units s
Notes 15, 16
Figure 14. Software Sequence Commands
33 33
Notes 14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete. 15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 16. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
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STK14CA8
Mode Selection
E H L L L W X H L H G X L X L A16-A0 X X X 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active Active Active 17, 18, 19 Notes
L
H
L
Active 17, 18, 19
L
H
L
Active
17, 18, 19
ICC2 Active 17, 18, 19
Notes 17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. 18. While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes 19. I/O state depends on the state of G. The I/O table shown assumes G low
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STK14CA8
nvSRAM Operation
nvSRAM
The STK14CA8 nvSRAM has two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates similar to a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited read and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
on page 3 for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. Figure 15. AutoStore Mode
VCC
10k Ohm
VCAP
VCC
SRAM READ
The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs are valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs repeatedly responds to address changes within the tAVQV access time without the need for transitions on any control input pins, and remains valid until another address change or until E or G is brought high, or W and HSB is brought low.
VCAP
W
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 are written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry turns off the output buffers tWLQZ after W goes low.
Hardware STORE (HSB) Operation
The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pull up and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 continues to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it is allowed a time tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes low are inhibited until HSB returns high. If HSB is not used, it should be left unconnected.
AutoStore Operation
The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Cypress Quantum Trap technology is enabled by default on the STK14CA8. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 15 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Characteristics
Hardware RECALL (Power Up)
During power up or after any low power condition (VCCDocument Number: 001-51592 Rev. **
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0.1F
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STK14CA8
Software STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. After a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. To initiate the software STORE cycle, the following READ sequence must be performed: Read Address Read Address Read Address Read Address Read Address Read Address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle
Data Protection
The STK14CA8 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCCNoise Considerations
The STK14CA8 is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are a short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed: Read Address Read Address Read Address Read Address Read Address Read Address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle

The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power up boot firmware routines should rewrite the nvSRAM into the desired state such as AutoStore enabled. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on.) If AutoStore is firmware disabled, it does not reset to "AutoStore enabled" on every power down event captured by the nvSRAM. The application firmware should re-enable or re-disable AutoStore on each reset sequence based on the behavior desired. The Vcap value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Cypress to understand any impact on the Vcap voltage level at the end of a tRECALL period.
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements.
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STK14CA8
Low Average Active Power
CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current is drawn as the memory cycle time becomes longer than 50 ns. Figure 16 shows the relationship between ICC and READ/WRITE cycle time. Worst case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for operations 3. The ratio of READs to WRITEs 4. The operating temperature 5. The VCC Level 6. I/O Loading Figure 16. Current vs Cycle Time
Preventing AutoStore
The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed: Read Address Read Address Read Address Read Address Read Address Read Address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Disable
The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed: Read Address Read Address Read Address Read Address Read Address Read Address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
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STK14CA8
Ordering Information STK14CA8-R F 45 ITR
Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
Ordering Codes
Part Number STK14CA8-NF25 STK14CA8-NF35 STK14CA8-NF45 STK14CA8-NF25TR STK14CA8-NF35TR STK14CA8-NF45TR STK14CA8-RF25 STK14CA8-RF35 STK14CA8-RF45 STK14CA8-RF25TR STK14CA8-RF35TR STK14CA8-RF45TR STK14CA8-NF25I STK14CA8-NF35I STK14CA8-NF45I STK14CA8-NF25ITR STK14CA8-NF35ITR STK14CA8-NF45ITR STK14CA8-RF25I STK14CA8-RF35I STK14CA8-RF45I STK14CA8-RF25ITR STK14CA8-RF35ITR STK14CA8-RF45ITR Description 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 Access Times 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
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STK14CA8
Package Diagrams
Figure 17. 32-Pin 300 mil SOIC (51-85127)
51-85127 *A
Figure 18. 48-Pin 300 mil SSOP (51-85061)
51-85061 *C
Document Number: 001-51592 Rev. **
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STK14CA8
Document History Page
Document Title: STK14CA8 128Kx8 AutoStoreTM nvSRAM Document Number: 001-51592 Revision ** ECN 2665610 Orig. of Change GVCH/PYRS Submission Date 02/04/09 New data sheet Description of Change
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51592 Rev. **
Revised March 04, 2009
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AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of their respective holders.
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